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Intel announces 45nm breakthrough
In a nutshell, Intel has announced a pair of advances in their 45nm process that will cut down drastically on leakage current (see below for more), enabling the company to make the transistors on their next generation of chips much smaller without worrying so much about current bleeding through when the transistor is in the “off” position. The first of these advances is the use of a high-k gate dielectric, a first in commercial semiconductor production. The dielectric is essentially an insulator that can now be made very thin without allowing electrical current to seep through (due to quantum tunneling) when the transistor is in the “off” position.

To complement this high-k dielectric, Intel has also moved to a metal gate electrode. This metal gate electrode is more compatible with the new hafnium-based dielectric than the polysilicon electrode used in previous process steps.

The new 45nm process will be used for Intel’s forthcoming Penryn microarchitecture, which is basically just a die shrink of Woodcrest with more cache.

According to David Kanter at RealWorldTech, IBM and AMD don’t plan to move to a similar high-k dielectric until the 32nm process node, a decision that may put them at a disadvantage versus Intel at 45 nanometers. Kanter summarizes the situation as follows:

The high-k dielectrics and metal gates will give Intel an advantage on their 45nm process. However, this transistor level advantage will not directly translate to microprocessor performance, without corresponding advances or clever engineering to address wire delay. It will be up to Intel’s MPU designers and marketers to make the most of these benefits, by increasing clock speed or reducing power. The real question is whether the combination of high-k dielectrics and metal gates will shut the window of opportunity for AMD, when they introduce their own 45nm process in mid to late 2008, and only time will tell where the chips will fall.

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